SRAM is commonly used in applications where speed and low power are considerations. SRAM cells are fast and do not need to be dynamically updated, as in the case of Dynamic Random Access Memory (DRAM) cells. The structure of a conventional SRAM cell comprises two cross-coupled inverters, commonly formed from four Complementary Metal Oxide Semiconductor Field-Effect Transistors (Complementary MOSFET or CMOS transistors). The cross-coupled inverters form the basic storage element, with two stable states which represent the complementary binary values “0” and “1”. Two additional transistors, called “access transistors”, serve to control access to the storage element during read and write operations. Accordingly, a conventional SRAM cell architecture involves six transistors, and is generally referred to as a 6T SRAM cell.
FIG. 1 illustrates a conventional 6T SRAM cell 100. The storage element comprises transistors M1-M4. Nodes Q and QC hold complementary binary values. A write operation on cell 100 is initiating by driving word line WL to positive power supply voltage VDD. Access transistors M5 and M6 convey the values on complementary bit lines BL and BLC into the storage element. In a read operation, BL and BLC are both pre-charged to a predefined value, or left floating. Once the word line is activated, the complementary values stored in the storage element act to discharge one of the bit lines. Sense amplifiers (not shown) quickly drive the values on the discharged bit line to negative power supply voltage VSS and the complementary bit line to VDD accordingly.
With shrinking device sizes, MOSFETs employed in conventional SRAM architectures suffer from short-channel effects such as increased subthreshold leakage currents. Further, as supply voltage and threshold voltages are lowered to keep power consumption low, the stability of data stored in the SRAM cell is affected. In order to combat the drawbacks of conventional MOSFET structures, Multigate Field Effect Transistors (MuGFETs) have been explored in the past. A MuGFET incorporates more than one gate in a single device, such that multiple gates may be controlled by a single gate electrode. The channel in such a multigate device is surrounded by several gates, leading to a suppression of leakage currents, and corresponding decrease in power consumption. While conventional MOSFETs are planar, the multigate devices are non-planar structures.
A FinFET is a multigate device, wherein the channel is wrapped around a thin silicon “fin”, which forms the body of the device (rather than a planar Si surface). The dimensions of the fin determine the effective channel length of the device. Short-channel effects are suppressed by making the fin very narrow. An independent-gate (IG) FinFET resembles two single-gate MOSFETs connected in parallel, sharing a common body.
Several parameters are relevant to studying the stability of SRAM cells. While these parameters will be initially explained with respect to the conventional SRAM cell of FIG. 1, they are easily extendable to IG-FinFET SRAM structures. Transistors M2 and M4 comprise a pull-up (PU) logic that enable the storage nodes Q and QC to be pulled up to positive supply voltage VDD. Similarly, transistors M1 and M3 comprise pull down (PD) logic to connect the nodes Q and QC to negative power supply voltage VSS (VSS may be connected to ground voltage). Access transistors M5 and M6 are also referred to as pass gate (PG) transistors. The relative strengths of PU, PD and PG components of an SRAM cell determine factors such as writability and data stability of the cell. In general, the strength of a transistor refers to the magnitude of current flowing through the device, and is proportional to the transistor size and gate voltage of the transistor.
Leakage currents, voltage perturbations, switching activity on neighboring cells and such other system noise have an effect on the stability of data in the SRAM cells. Sometimes the noise may be high enough to cause the data stored in a cell to “flip” to a false state, even if the particular cell is not selected for a read or write operation. The minimum DC-voltage disturbance required to upset or flip the state of a cell is known as the Static Noise Margin (SNM). Hold Static Noise Margin (HSNM) refers to the SNM of a cell in hold or standby mode. With reference to FIG. 1, increasing VDD-Cell voltage generally has the effect of increasing HSNM.
Parameter “α” denotes the ratio of strengths of PG and PU (represented as “PG/PU”). It can be seen that decreasing the PU strength and increasing the PG strength allows the values on BL and BLC to be easily written into the storage nodes. Write static Noise Margin (WNM) refers to the SNM of a cell in write mode. Accordingly, the WNM of an SRAM circuit varies in proportion with α. As indicated by α(=PG/PU) the WNM can be improved by increasing PG and/or decreasing PU.
Parameter “β” denotes the ratio of strengths of PD and PG (represented as “PD/PG”). It can be seen that decreasing the PG strength and increasing the PD strength allows the values on Q and QC to be easily read into the bit lines. Read Static Noise Margin (RSNM) refers to the SNM of a cell in read mode. The RSNM of an SRAM circuit varies in proportion with β. As indicated by β(=PD/PG), the RSNM can be improved by increasing PD and/or decreasing PG.
From the foregoing discussion, it will be understood that varying the strengths of the PU, PD and PG components involves a complex tradeoff between the HSNM, RSNM and WNM of the cell. FIG. 2A illustrates a conventional tied-gate SRAM (TG-SRAM) cell including a pair of bit lines denoted “bitline” and “bitline_b” and a word line denoted “wordline.” TG-SRAM cells have the basic structure of a dual-gate SRAM (DG-SRAM) cell. Both gates in the dual-gate of each transistor in TG-SRAM are tied together and thus the operation of a TG-SRAM cell is similar to that of a conventional 6T SRAM in FIG. 1.
A technique to increase cell stability by a feedback mechanism to back gates of the PG devices is proposed in Guo et al., “FinFET-Based SRAM Design”, Symp. ISLPED, 2005, pp 2-7 (hereinafter, “Guo”), which is incorporated herein by reference. Guo utilizes a FinFET based SRAM cell that includes a pair of bit lines denoted “bitline” and “bitline_b” and a word line denoted “wordline” in order to gain better control over the gates and lower subthreshold leakage currents as noted above. Guo attempts to improve the cell β ratio by controlling the back gate of the PG devices. The back gates of the PG devices are controlled by connecting the storage nodes to the back gates, as illustrated in FIG. 2B, in order to improve RSNM. However, connecting the storage nodes to the back gates deteriorates WNM by reducing the cell α ratio. In order to improve the WNM, Guo proposes lowering the voltage, VDD-Cell.
FIG. 3 illustrates a schematic of an SRAM array formed by cells according to Guo. Bit lines BL and BLB are shown to be disposed in a vertical direction in FIG. 3, while the word lines WL are disposed in a horizontal direction. The VDD-Cell of the cells, selected cell 31, connected to the “selected” BL and BLB (i.e. BL=1, BLB=0, and WL=1) is lowered during the write operation, thereby reducing the PU drive strength. As a result, the α ratio (PG/PU) of the selected cell is improved.
However, VDD-Cell of the half selected cell 32 (horizontally selected and vertically unselected, i.e. WL=1, BL and BLB=floating voltage of value 1 or “f1”) in FIG. 3 is also reduced, which has the effect of lowering HSNM fir the half selected cell 32. Therefore, while Guo attempts to improve WNM of the SRAM cell, the HSNM deteriorates. Accordingly, there are two drawbacks in the design of Guo. Firstly, controlling VDD-Cell is very hard, and is subject to a lot of variation in the SRAM array. Secondly, lowering VDD-Cell has the effect of lowering HSNM, as noted above.
FIG. 7 illustrates butterfly transfer curves (BTC) for calculating a RSNM of conventional TG-SRAM cells (51.1 mV) and the RSNM of SRAM cells of Guo (136.5 mV). A. BTC is a plot of the storage node voltage during a read operation, a write operation, or a standby mode. The SNM (e.g., the RSNM, the WNM, or the HSNM) is measured by the largest square that fits inside the BTC. As indicated by FIG. 7, the circuit of Guo offers an improvement in RSNM of 85.4 mv as compared to conventional TG-SRAM circuits. FIG. 8 similarly illustrates BTCs for calculating a WNM of the conventional TG-SRAM cells (338.5 mV) and the SRAM cells of Guo (372 mV). It can be observed that the circuit of Guo offers an improvement in WNM of 34.1 mv due to the lowering of VDD-Cell voltage. FIG. 9 illustrates BTCs for calculating an HSNM of the conventional TG-SRAM cells (324.5 mV) and for the SRAM cells of Guo (283.1 mV). It is observed that the HSNM of the SRAM cells of Guo is 41.4 mv lower than the HSNM of the conventional TG-SRAM cells.
An alternate scheme has been proposed to address the issues of conventional TG-SRAMs and Guo, in Liu et al., “An Independent-Gate FinFET SRAM Cell for High Data Stability and Enhanced Integration Density”, IEEE SOC Conference, 2007, pp. 68-69, (hereinafter, “Liu”), which is incorporated herein by reference. The SRAM cell of Liu is illustrated in FIG. 4 and includes a pair of bit lines denoted “bitline” and “bitline_b.” Liu utilizes a FinFET based structure, wherein each of the PU, PD and PG components utilize two transistors with independently controllable gates. This provides for improved control over their respective strengths.
Liu uses the control signals “RW” and “W”, as shown in FIG. 4, to control read and write operations, instead of a conventional word line control signal (e.g., WL in FIG. 1). The Signal RW is held high during both read and write operations, while the signal W is high only during a write operation. Thus during a read, RW is high and W is low. Accordingly, during a read, PG1 and PG2 are conducting, but with the strength of only one of the two transistors (front transistor) in each pair, enabling PG to be maintained at a low value. PD and PU (i.e. PD1, PD2, PU1 and PU2) are maintained at a constant value, and therefore β(=PD/PG) is caused to increase, and RSNM of the cell is correspondingly high.
During a write operation in Liu, both RW and W are high, causing both transistors in each pair PG1 and PG2 to be conducting. It will be seen in this mode, that the relative strengths of the PU, PD and PG components of the cell are similar to that of a conventional SRAM, since each component in Liu is essentially replaced by a pair of transistors, as compared to a single transistor in conventional SRAMs. Therefore the ratio, α(=PG/PU) is comparable to that of a conventional TG-SRAM, and correspondingly, there is no improvement in the WNM of Liu. In a standby mode, both RW and W signals remain low, and thereby the HSNM of Liu is the same as that of a conventional TG-SRAM.
While the techniques provide improvements in one or two of these parameters, it is at the cost of either deterioration and/or lack of improvement in the remaining parameters. Therefore there is a need in the art for techniques to improve the SNM of SRAM circuits in read, write modes of operation without degrading the stability in standby mode of operation.